Generally, a plurality of devices (e.g., transistors, diodes, etc.) are designed and embedded into an integrated circuit (IC) chip/die, which may be placed into a package (e.g., plastic casing) or used as a bare die for placement onto a printed circuit board (PCB) of an electronic device. However, due to limited space availability on the PCBs, manufacturers of the IC chips are integrating multiple IC chips into a single vertical three-dimensional (3D) IC chip stacks, which require a much smaller footprint on a PCB. For example, a 3D IC chip stack may include several logic, memory, analog, or similar IC chips that may be connected to each other by using of TSV architecture. Typically, TSVs are vertical vias etched in a silicon layer and filled with a conducting material (e.g., copper), which provides connectivity for communication signals and voltage supply between the vertically stacked IC chips. Adoption of 3D IC chip stacking is increasingly being viewed as an alternative or addition to traditional technology node scaling at the transistor level, which may provide solutions to meet performance, power, and bandwidth requirements of various electronic devices.
FIGS. 1A and 1B schematically illustrate example of IC chip structure including a plurality of TSVs. FIG. 1A illustrates an example of 3D IC chip stack 100 that includes IC chips 101, 103, and 105. These chips are “sandwiched” and interconnected by interconnection layers 107 (e.g., including micro-bumps) to form a vertical stack, which is connected to a package substrate 109. As illustrated, the IC chips 101 and 103 may include a front metal layer 111 and a back metal layer 113, but the IC chip 105 includes only a front metal layer 111, wherein each of the metal layers 111 and 113 may represent a plurality of metal layers M-1 through M-n. Additionally, the IC chips 101, 103, and 105 include a device layer 115 and a silicon layer 117. FIG. 1B illustrates the single IC chip 101, which still includes the plurality of TSVs 119. In various scenarios, the TSVs may be implemented by use of different IC manufacturing processes; however, implementation of TSVs in 3D IC chip stacks, as well as in a single IC chip, can cause defects in the IC chip stack or in the single IC chip. For instance, implementation of the TSVs may introduce defects affecting the electrical performance of components/devices embedded in an IC chip, or the TSVs may impact the reliability of an IC chip stack. For the sake of an example, fully processed wafers with chips manufactured on top are lapped and their thickness reduced down to few microns. In some other instances, the defects may be due to a back-end-of-line (BEOL) process where an IC chip stack is formed or due to mounting of an IC chip wafer (e.g., including a plurality of IC chips) onto a plastic substrate. To quantify possible defects, various parameters at an IC chip may be measured and characterized while the IC chip wafer is cycled through different temperatures and defects may be more visible in a specific temperature range. However, increasing the temperature of an entire chip wafer may be time consuming, and the plastic substrate/film of a thinned IC chip wafer (e.g., 50 micrometer) may not be able to withstand higher temperatures (e.g., more than 50° Celsius (C)) of a test environment.
Therefore, a methodology and circuitry enabling both the defects detection due to TSVs processing damage as well as measuring various parameters associated with an IC chip on a plastic carrier is highly needed.